1. Field of the Invention
The present invention relates to a semiconductor memory device incorporating redundancy memory cells having a parallel test function, and more particularly, an improvement of a redundancy decoder portion thereof.
2. Description of the Related Art
In a prior art semiconductor memory device incorporating redundancy memory cells, one redundancy decoder is provided in the periphery of each normal decoder for activating memory cells of a memory cell block. In other words, the number of redundancy decoders is the same as that of normal decoders. Therefore, if a defective memory cell is found in one memory cell block, an address of a defective memory cell is written into the corresponding redundancy decoder of the same memory cell block by laser trimming or the like. As a result, when such a defective address is received by the redundancy decoder, the redundancy decoder deactivates its corresponding normal decoder and in its place, selects the redundancy memory cell, to thereby replace the defective memory cell with the redundancy memory cell. Thus, the defective memory cell is alleviated.
On the other hand, as the integration of semiconductor memory devices has developed, a marching test, where "1" (or "0") is sequentially written into all of the memory cells and after that, data is sequentially read therefrom, requires a considerable time such as 10 s in the case of a 4 Mbit dynamic random access memory (DRAM). Therefore, in order to reduce a test time, a parallel test such as the "JEDEC standard" has been adopted. For example, in a 4 Mbit DRAM, "1" (or "0") is simultaneously written into 32 memory cells, and after that, data is simultaneously read therefrom. As a result, if the read data fails to coincide, a common address between the 32 memory cells, i.e., a degenerate address is written into the corresponding redundancy decoders, thereby to replace all the 32 memory cells with their corresponding redundancy memory cells.
In the parallel test for the prior art semiconductor memory device, however, since each of the redundancy decoders is provided for one of the memory cell blocks, the degenerate address is written into each of the redundancy decoders for the memory cell blocks to which the 32 memory cells belong to. That is, if the 32 memory cells belong to four memory cell blocks, the writing operation of the degenerate address is performed upon four locations of the redundancy decoders, in other words, this writing operation is carried out four times, which increases the test time. This will be explained in detail later.